The present invention relates to a monolithic semiconductor device in which a MOSFET is incorporated in a chip to provide zero cross function, and to a manufacturing method thereof.
There has been no prior art for the method of producing gate insulating film of an AC 200V zero cross photo triac. The localized oxidation of oxygen doped polycrystalline silicon film for producing MOS-IC gate insulating film may be considered as an equivalent technique. As indicated in FIG. 2, the localized oxidation process comprises the steps of diffusing a silicon wafer 10, removing the entire SiO.sub.2 film from the semiconductor substrate surface, depositing an oxygen doped polycrystalline silicon film 11 and a SiO.sub.2 film formed through chemical vapor deposition (hereinafter abbreviated as CVD SiO.sub.2 film) 12 successively, removing the CVD SiO.sub.2 film 12 selectively by photo-etching and wet-etching, and thermally oxidizing the oxygen doped polycrystalline silicon film 11 in the surface area from which the CVD SiO.sub.2 film 12 has been removed. The SiO.sub.2 film 12 used as a MOS gate insulating film (indicated by 13) is produced by the above process. Meanwhile, the oxygen doped polycrystalline silicon film in the area where the CVD SiO.sub.2 film 12 is left unremoved will remain unoxidized due to the thickness of the CVD SiO.sub.2 film 12. The passivation effect is therefore retained.
With the above conventional method in which the oxygen doped polycrystalline silicon film 11 is thermally oxidized after being deposited, the silicon grain size in the oxygen doped polycrystalline silicon film 11 changes during the oxidation process at a high temperature (T=1,100.degree. C. or higher), causing reduced passivation effect and increased leak current in the P-N junction. Accordingly, permitted gate oxidizing temperature and time are restricted below 1,100.degree. C. and below 30 minutes, which limits the oxide film thickness to 2,000.about.3,000 .ANG. at maximum.
The limited oxide film thickness is a fatal barrier for realizing a MOSFET which requires high gate insulation breakdown voltage resistance.